A chip stacking technology utilizing transmission line coupling

Author

Iguchi, Daisuke ; Akiyama, Yutaka ; Ito, Tsuneo ; Otsuka, Kanji

Author_Institution

Fuji Xerox Co., Ltd., Ebina

fYear

2008

fDate

1-2 Dec. 2008

Firstpage

77

Lastpage

80

Abstract

Presented in this paper is a new chip stacking technology for very high bandwidth communication. This technology utilizes transmission line coupling between two differential pairs in the metal layers of the stacked LSI chips. We have demonstrated communication at 12.5 GHz between two differential pairs of transmission lines fabricated on different metal layers in a single chip. This technology is expected to realize contactless interconnects between stacked LSI chips without changing conventional LSI fabrication process leading to higher yield, lower cost, and higher reliability.

Keywords

chip scale packaging; coupled transmission lines; interconnections; large scale integration; reliability; stacking; LSI chips; chip stacking; contactless interconnects; frequency 12.5 GHz; reliability; transmission line coupling; Bandwidth; CMOS technology; Communications technology; Couplings; Crosstalk; Large scale integration; Power transmission lines; Stacking; Testing; Transmission lines;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Packaging Workshop of Japan, 2008. VPWJ 2008. IEEE 9th

Conference_Location

Kyoto

Print_ISBN

978-1-4244-3498-5

Type

conf

DOI

10.1109/VPWJ.2008.4762212

Filename

4762212