A new low-cost method for identifying untestable path delay faults

In many designs a large portion of path delay faults is non-robustly untestable. This paper presents a new low-cost method for identifying non-robustly untestable path delay faults. Using an implication-based procedure, our method starts with a small number of path segments, called maximum fanout-free segments, to quickly locate lines which cannot construct non-robustly testable paths with them. After a large portion of faults is marked as untestable, only a small subset of faults remains for the ATPG procedure, which can effectively alleviate the problem of handling a huge number of path delay faults and reduce test generation time. Experimental results for ISCAS´85 benchmark circuits demonstrate that a significant portion of non-robustly untestable path delay faults was identified efficiently using our method. For most of these circuits, 90%-95% of non-robustly untestable path delay faults can be identified within a small amount of CPU time