Title :
MPS-C2 and Post Encapsulation Grinding technology for ultra fine pitch and thin die flip chip applications
Author :
Orii, Yasumitsu ; Toriyama, Kazushige ; Oyama, Yukifumi ; Nishio, Toshihiko
Author_Institution :
Packaging Technol. Solution Dev., Kyoto
Abstract :
Flip chip technology is now being introduced in PoP(Package on Package) packages for the digital consumer electronics such as digital still cameras and mobile phones. PoP reduces the component height and improves the electrical performance. A MPS-C2(Metal Post Solder Chip Connection) method was developed for ultrafine pitch flip chip interconnections in mobile applications. A bare die with Sn/Ag-solder-capped Cu post bumps is directly connected on an organic substrate by using a reflow process without flux cleaning. This technology supports the SMT/Flip Chip-hybrid assembly required for SoP (System on Package) manufacturing, and it is the least expensive method among current ultrafine pitch flip chip interconnetion methods. We ran reliability tests with 50-um-pitch MPS-C2 interconnections. In addition to fine pitch interconnections, each die must be less than 70 um thick to insure that the final stack will be thin enough. Such thin die were not unsuitable for the original MPS-C2 process, because the dies tended to move during the reflow process. We developed a Post Encapsulation Grinding (PEG) method to resolve this problem. In this method the die is ground down to be less than 70 um thick after joining and underfilling.
Keywords :
encapsulation; flip-chip devices; grinding; hybrid integrated circuits; integrated circuit interconnections; solders; system-on-package; chip-hybrid assembly; digital electronics; digital still cameras; flip chip technology; flux cleaning; joining; metal post solder chip connection; mobile phones; post encapsulation grinding; reflow process; ultrafine pitch flip chip interconnections; underfilling; Assembly systems; Cleaning; Consumer electronics; Digital cameras; Electronics packaging; Encapsulation; Flip chip; Mobile handsets; Surface-mount technology; Tin;
Conference_Titel :
VLSI Packaging Workshop of Japan, 2008. VPWJ 2008. IEEE 9th
Conference_Location :
Kyoto
Print_ISBN :
978-1-4244-3498-5
DOI :
10.1109/VPWJ.2008.4762218