DocumentCode
2496502
Title
On the determination of threshold voltages for CMOS gates to facilitate test pattern generation and fault simulation
Author
Lee, Kuen-Jong ; Tang, Jing-Jou ; Duh, Wern-Yih
Author_Institution
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
fYear
1998
fDate
2-4 Dec 1998
Firstpage
113
Lastpage
118
Abstract
An accurate threshold voltage determination method for CMOS gates is presented that can be used to enhance the performance of test pattern generation (TPG) and fault simulation (FS). By using this model the “Byzantine General” problem during the FS and TPG can be overcome. Experimental data show that SPICE like accuracy can be achieved without carrying out circuit-level simulation
Keywords
CMOS digital integrated circuits; CMOS logic circuits; automatic test pattern generation; fault simulation; integrated circuit testing; logic gates; logic testing; ATPG; Byzantine General problem; CMOS digital logic; CMOS gates; fault simulation; test pattern generation; threshold voltage determination; CMOS logic circuits; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Equations; SPICE; Semiconductor device modeling; Test pattern generators; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 1998. ATS '98. Proceedings. Seventh Asian
ISSN
1081-7735
Print_ISBN
0-8186-8277-9
Type
conf
DOI
10.1109/ATS.1998.741600
Filename
741600
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