Automated debugging with high level abstraction and refinement

Design debugging is a manual and time consuming task which takes as much as 60% of the verification effort. To alleviate the debugging pain automated debuggers must tackle industrial problems by increasing their capacity and improving their performance. This work introduces an abstraction and refinement methodology for debugging that leverages the high level information inherent to RTL designs. Function abstraction uses the modular nature of designs to simplify the debugging problem. If required, refinement re-introduces the necessary circuitry back into the design in order to find all error locations. The abstraction and refinement process is applied throughout the design´s hierarchy allowing for a divide and conquer methodology. The proposed technique is shown to reduce the memory requirement by as much as 27 x and reduce the run-time by two orders of magnitude over a conventional debugger.