STAR: Generating input vectors for design validation by static analysis of RTL

We introduce STAR, an automatic technique for functional input vector generation for design validation. STAR statically analyzes the source code of the Register Transfer Level (RTL) design. The STAR approach is a hybrid between RTL symbolic simulation and concrete simulation, that offsets the disadvantages of both the techniques. It allows deeper as well as wider exploration of the design space by varying the extent of concrete and symbolic simulation in a given run. STAR follows a region-wide notion of coverage, where the concrete simulation navigates to a region of the design space and the symbolic simulation explores it systematically. We demonstrate that preliminary results of using STAR are promising by showing high path coverage on benchmark RTL designs.