Title :
A non-scan DFT method for controllers to achieve complete fault efficiency
Author :
Ohtake, Satoshi ; Masuzawa, Toshimitsu ; Fujiwara, Hideo
Author_Institution :
Graduate Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Japan
Abstract :
This paper presents a non-scan design-for-testability method for controllers that are synthesized from FSMs (Finite State Machines). The proposed method can achieve complete fault efficiency: test patterns for a combinational circuit of a controller are applied to the controller using state transitions of the FSM. In the proposed method, at-speed test application can be performed and the test application time is shorter than previous methods. Moreover, experimental results show the area overhead is low
Keywords :
VLSI; automatic testing; combinational circuits; design for testability; fault diagnosis; finite state machines; integrated circuit testing; FSMs; area overhead; at-speed test application; combinational circuit; design-for-testability method; fault efficiency; finite state machines; nonscan DFT method; state transitions; test application time; Circuit faults; Circuit testing; Combinational circuits; Costs; Design for testability; Design methodology; Logic testing; Registers; Sequential analysis; Sequential circuits; Test pattern generators;
Conference_Titel :
Test Symposium, 1998. ATS '98. Proceedings. Seventh Asian
Print_ISBN :
0-8186-8277-9
DOI :
10.1109/ATS.1998.741615
