A self-timed two-stage flexible ALU implementation

Author

Yuan-Teng Chang ; Chiou-Ching Fang ; Hung-Yue Tsai ; Cheng, Wei-min ; Chang-Jiu Chen ; Fu-Chiung Cheng

Author_Institution

Dept. of Comput. Sci., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

2012

fDate

2-5 Oct. 2012

Firstpage

378

Lastpage

381

Abstract

SOCs designed for embedded systems are now widely used on embedded multimedia devices. Processors in these devices may need capabilities to support some compound computations, and the most important of all is multiply and accumulate (MAC) operation. Thus DSP processors or special ALUs are designed to accelerate these computations. Besides the computation issue, how to improve the reliability, stability and power efficiency is also very important. It´s well-known that asynchronous circuit can be used to address these issues. Thus, in this paper, we propose a dual-rail two-stage flexible ALU to achieve these goals. We also show the delay time for possible operation combinations.

Keywords

digital signal processing chips; embedded systems; integrated circuit design; system-on-chip; DSP processors; MAC; SOC design; compound computations; embedded multimedia devices; embedded systems; multiply and accumulate operation; self timed two stage flexible ALU implementation; Asynchronous circuits; Compounds; Computers; Delay; Logic gates; Multimedia communication; Program processors; ALU; Asynchronous circuit; SOC; Self-Timed;

fLanguage

English

Publisher

ieee

Conference_Titel

Consumer Electronics (GCCE), 2012 IEEE 1st Global Conference on

Conference_Location

Tokyo

Print_ISBN

978-1-4673-1500-5

Type

conf

DOI

10.1109/GCCE.2012.6379633

Filename

6379633