Title :
Verification of asynchronous circuits with bounded inertial gate delays
Author :
Gong, J. ; Wong, Eddie M C
Author_Institution :
Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore
Abstract :
Verifying the correctness of asynchronous circuits is one of the most important task in asynchronous design. However, the absence of the global clock and the variation of gate delays in asynchronous circuits makes the verification a formidable task. In this paper, a verification method which can cover all the deviation of gate-level implementation of an asynchronous circuit from the specified behavior given by the STG is proposed. The ternary logic is used in order to describe the behaviors of gates with bounded inertial delays
Keywords :
asynchronous circuits; delays; formal verification; hazards and race conditions; logic CAD; signal flow graphs; ternary logic; STG; asynchronous circuits; bounded inertial gate delays; gate-level implementation; signal transition graph; ternary logic; Asynchronous circuits; Circuit simulation; Circuit synthesis; Circuit testing; Clocks; Delay; Design engineering; Hazards; Multivalued logic; Packaging; Signal generators;
Conference_Titel :
Test Symposium, 1998. ATS '98. Proceedings. Seventh Asian
Print_ISBN :
0-8186-8277-9
DOI :
10.1109/ATS.1998.741646
