Analysis of noise margin of CMOS inverter in sub-threshold regime

In this paper, the Noise margin parameters of a CMOS inverter circuit in sub-threshold regime have been analyzed thoroughly with respect to variable supply voltage, transistor strength and temperature; without neglecting the significant DIBL and body bias effects. In particular, the change in the DC characteristics shape due to operation at ultra-low voltages is analyzed in detail, evaluating analytically the degradation in the logic swing, the symmetry and the steepness of the transition region, as well as the change in the unity-gain points and logic threshold points. Extensive simulations have been done under 45 nm CMOS technology using CADENCE Spice spectra to ensure the correctness of the analysis.