DocumentCode
2497538
Title
Comparative analysis of delay for sub-threshold CMOS logics
Author
Jain, Sonal ; Chanda, Manash ; Sarkar, Chandan K.
Author_Institution
Dept. of Electron. & Commun. Eng., Meghnad Saha Inst. of Technol., Kolkata, India
fYear
2013
fDate
12-14 April 2013
Firstpage
1
Lastpage
4
Abstract
In this paper, the propagation delays of various MOSFET structures in the sub-threshold regime is calculated for a 22nm MOSFET and a comparative analysis of the delays is presented. The sensitivity of the propagation delay to supply voltage and temperature is also put forward in this paper. The EKV model of MOSFET is used to describe the sub-threshold conduction current, taking into account the body-drain, body-source potential dependencies.
Keywords
CMOS logic circuits; delays; EKV model; MOSFET structure; body-drain potential dependency; body-source potential dependency; comparative analysis; delay analysis; propagation delay; size 22 nm; subthreshold CMOS logic; subthreshold regime; supply voltage; CMOS integrated circuits; Delays; Integrated circuit modeling; MOSFET; Propagation delay; Sensitivity; DTMOS; delay; invertor; sensitivity; sub-threshold;
fLanguage
English
Publisher
ieee
Conference_Titel
Engineering and Systems (SCES), 2013 Students Conference on
Conference_Location
Allahabad
Print_ISBN
978-1-4673-5628-2
Type
conf
DOI
10.1109/SCES.2013.6547500
Filename
6547500
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