Title :
A self-aligned inverse-T gate fully overlapped LDD device for sub-half micron CMOS
Author :
Wen, D.S. ; Hsu, C.C.-H. ; Taur, Y. ; Zicherman, D.S. ; Wordeman, M.R. ; Ning, T.H.
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
A novel self-aligned technique for fabricating inverse-T gate fully overlapped LDD (FOLD) MOSFETs is proposed. The technique uses an oxide or TiN buffer layer sandwiched in a polysilicon gate stack to act as an RIE (reactive ion etching) etch stop. Both the oxide and TiN exhibit good etch selectivities with respect to polysilicon. Therefore, a controllable, uniform polysilicon finger can be obtained to form the inverse-T structure. A 0.35- mu m n-channel inverse-T gate MOSFET with fully overlapped LDD (lightly doped drain) design has been fabricated and characterized. It is found that the inverse-T LDD device preserves the performance of a non-LDD device while providing reliability improvement similar to that of a conventional LDD device. The inverse-T LDD device is suitable for high-performance, high-reliability sub-half-micron device applications.<>
Keywords :
CMOS integrated circuits; integrated circuit technology; reliability; sputter etching; 0.35 micron; CMOS; MOSFETs; RIE etch stop; TiN buffer layer; etch selectivities; fully overlapped LDD device; high-performance; high-reliability; inverse-T structure; lightly doped drain; polycrystalline Si; polysilicon; reactive ion etching; reliability improvement; self-aligned inverse-T gate; sub-half-micron device; Buffer layers; Conductivity; Etching; Fingers; MOSFETs; Oxidation; Plasma applications; Plasma immersion ion implantation; Reproducibility of results; Tin;
Conference_Titel :
Electron Devices Meeting, 1989. IEDM '89. Technical Digest., International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-0817-4
DOI :
10.1109/IEDM.1989.74166
