ASIC Design of Reversible Multiplier Circuit

Reversible logic is very much in demand for the future computing technologies as they are known to produce low power dissipation having its applications in Low Power CMOS, Quantum Computing, Nanotechnology, and Optical Computing. Adders and multipliers are fundamental building blocks in many computational units. In this paper we have presented and implemented reversible Wallace signed multiplier circuit in ASIC through modified Baugh-Wooley approach using standard reversible logic gates/cells, based on complementary pass-transistor logic and have been validated with simulations, a layout vs. Schematic check, and a design rule check. It is proved that the proposed multiplier is better and optimized, compared to its existing counterparts with respect to the number of gates, constant inputs, garbage outputs, hardware complexity, and number of transistors required. It has also been shown in Cadence´s tools that the reversible multiplier outperform the irreversible multiplier in terms of power dissipation.