DocumentCode
2498466
Title
An integrated 0.5 mu m CMOS disposable TiN LDD/salicide spacer technology
Author
Pfiester, J.R. ; Parrillo, L.C. ; Woo, M. ; Kawasaki, H. ; Boeck, B. ; Travis, E. ; Gunderson, C.
Author_Institution
Motorola Inc., Austin, TX, USA
fYear
1989
fDate
3-6 Dec. 1989
Firstpage
781
Lastpage
784
Abstract
A novel disposable TiN LDD/salicide spacer process has been developed for a 0.5- mu m CMOS technology. Both LDD (lightly doped drain) and salicide definition are obtained using a single disposable TiN spacer. This process results in CMOS devices with low salicided junction leakage, reduced source/drain lateral diffusion, and shallow phosphorus n- and boron p-regions for improved short-channel behavior.<>
Keywords
CMOS integrated circuits; integrated circuit technology; ion implantation; metallisation; 0.5 micron; CMOS technology; Si:B; Si:P; disposable TiN LDD/salicide spacer technology; disposable TiN spacer; lightly doped drain; low salicided junction leakage; reduced lateral diffusion; salicide definition; shallow n-regions; shallow p-regions; short-channel behavior; Annealing; CMOS technology; Etching; Implants; MOS devices; MOSFET circuits; Rapid thermal processing; Space technology; Tin; Titanium;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1989. IEDM '89. Technical Digest., International
Conference_Location
Washington, DC, USA
ISSN
0163-1918
Print_ISBN
0-7803-0817-4
Type
conf
DOI
10.1109/IEDM.1989.74170
Filename
74170
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