An approach for downscaling images for real-time pattern detection

In this paper, we describe an approach for downscaling images for real-time pattern detection on FPGA. Using FPGAs, we can reconfigure specific circuits for given patterns, and detect various patterns efficiently with less hardware resources. In our approach, a sequence of downscaled images (downscaled by alpha^k (k = 0, 1, 2, ..., n)) is generated, and regions in each image are compared with fixed size templates in order to detect patterns of various sizes in the original image. In this downscaling process, we need to (1) maintain the quality of the downscaled images, (2) generate them in parallel with the pattern detection, and (3) minimize the unit size and the number of the external memory banks required for the downscaling. In our approach based on an area-averaging method, all downscaled images have the same quality as when generated from the original image, and the computation is completely overlapped with the pattern detection. The downscaling units for alpha³ = 1/2 occupy only 3% LUTs of Xilinx XC2V6000, and only one external memory bank is used for downscaling grayscale images.