Synthesis of efficiently reconfigurable datapaths for reconfigurable computing

We present new approach to optimize circuits for dynamic reconfiguration in FPGAs. Within a high level synthesis tool we optimize the binding of operations to resources to achieve high re-use of resources and interconnect between different configurations. We demonstrate that reconfiguration costs can be drastically reduced, while adding a small area overhead. Moreover, our method can merge several tasks into area efficient, static implementations. Both methods allow us to find new trade-offs between resource requirements and reconfiguration costs in dynamic application scenarios.