Title :
Scaling rules for bipolar transistors in BiCMOS circuits
Author :
Rosseel, G.P. ; Dutton, R.W.
Author_Institution :
Stanford Univ., CA, USA
Abstract :
Scaling rules for bipolar transistors in BiCMOS gates are derived such that the gates maintain their performance advantage over scaled CMOS implementations. These are compared with those for bipolar transistors in ECL (emitter coupled logic) gates and are found to be generally similar under realistic scaling assumptions, except for a conflict in the choice of the collector doping concentration. Bipolar transistors for BiCMOS drivers require a high collector doping concentration (typically higher than 5E16 cm/sup -3/) while ECL circuits require bipolar transistors with lower value for the collector doping concentration (typically lower than 2E16 cm/sup -3/).<>
Keywords :
BIMOS integrated circuits; bipolar transistors; emitter-coupled logic; integrated circuit technology; semiconductor doping; BiCMOS circuits; BiCMOS gates; bipolar transistors; collector doping concentration; emitter coupled logic; scaled CMOS implementations; scaling rules; BiCMOS integrated circuits; Bipolar transistors; CMOS memory circuits; CMOS process; CMOS technology; Capacitance; Delay; Doping; Inverters; MOSFETs;
Conference_Titel :
Electron Devices Meeting, 1989. IEDM '89. Technical Digest., International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-0817-4
DOI :
10.1109/IEDM.1989.74173
