• DocumentCode
    2499385
  • Title

    On the scaling property of trench isolation capacitance for advanced high-performance ECL circuits

  • Author

    Chuang, C.T. ; Lu, P.F.

  • Author_Institution
    IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
  • fYear
    1989
  • fDate
    3-6 Dec. 1989
  • Firstpage
    799
  • Lastpage
    802
  • Abstract
    A detailed study on the scaling property of trench isolation capacitance for advanced high-performance bipolar applications is presented. Using two-dimensional numerical simulations, it is shown that depending on the particular trench used, the trench isolation capacitance has a distinct dependence on the trench width. The impact on the scaled-down high-performance ECL circuits is examined. It is concluded that the design and optimization of scaled-down devices and circuits would require an in-depth understanding of the trench isolation parasitics to realize the full potential of advanced technology.<>
  • Keywords
    VLSI; bipolar integrated circuits; emitter-coupled logic; integrated circuit technology; VLSI; advanced high-performance ECL circuits; optimization; scaled-down devices; scaling property; trench isolation capacitance; trench isolation parasitics; trench width; two-dimensional numerical simulations; Admittance; Circuit optimization; Delay effects; Dielectrics; Filling; Isolation technology; Parasitic capacitance; Performance analysis;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting, 1989. IEDM '89. Technical Digest., International
  • Conference_Location
    Washington, DC, USA
  • ISSN
    0163-1918
  • Print_ISBN
    0-7803-0817-4
  • Type

    conf

  • DOI
    10.1109/IEDM.1989.74174
  • Filename
    74174