CMOS time-to-digital converter with low PVT sensitivity 20.8ps resolution and −0.25∼0.22 LSB inaccuracy

A simple but accuracy-enhanced CMOS time-to-digital converter (TDC) based on pulse stretcher interpolators is presented. Without the need of modifying the conventional circuit, both inaccuracy and PVT (process, voltage and temperature) sensitivity are substantially reduced. The errors caused by charge injection and clock feedthrough are eliminated by precise device sizing. The accuracy of current and capacitor ratios for its pulse stretchers is ensured by two-dimensional common centroid layouts. Fabricated in a TSMC 0.35 μm standard CMOS process, the time resolution can be realized as 20.8 ps and the INL error is proven to be -0.25~0.22 LSB for 0~20 ns input range. Moreover, the measured resolution merely spreads over 20.25~20.96 ps for twenty packaged chips. All fabricated chips were tested to be full functional under - 40~120°C temperature operation range and 2.6~4.9 V supply voltage range with about ten-fold improvement in temperature drift and supply voltage sensitivity from its predecessor´s.