A 1.5-bit pipelined stage with time-interleaved dual-pipeline architecture used in SHA-less pipelined ADC

Author

Wang, Yan ; Wang, Yuxin ; Liu, Tao ; Li, Ting ; Lan, Jinbao

Author_Institution

NO.24 Res. Inst., CETC, Chongqing, China

fYear

2011

fDate

24-26 June 2011

Firstpage

131

Lastpage

134

Abstract

A design of a 1.5-bit pipelined stage with time-interleaved dual-pipeline architecture used in SHA-less pipelined ADC is presented in this paper. Due to the absence of SHA, sampling flash architecture and bootstrapped sampling switch is used to improve the linearity. Op-amp sharing between time-interleaved dual-pipeline is to reduce power consumption. The sampling network is specially analyzed. The pipelined stage can be used as the first stage of a 10-bit 40 MHz pipelined A/D converter. Simulation by Spectra on 0.18um CMOS process under 1.8V supply voltage shows its SFDR achieves 62 dB near Nyquist input frequency.

Keywords

CMOS integrated circuits; analogue-digital conversion; operational amplifiers; sample and hold circuits; 0.18um CMOS process; 1.5-bit pipelined stage; SHA-less pipelined ADC; analog-to-digital converters; bootstrapped sampling switch is; frequency 10 MHz; near Nyquist input frequency; op-amp sharing; pipelined A/D converter; power consumption reduction; sample- and-hold amplifier; sampling flash architecture; time-interleaved dual-pipeline architecture; voltage 1.8 V; Bandwidth; Capacitors; Gain; Linearity; Pipelines; Power demand; Switches; Pipelined ADC; SHA-less; boostrapped switch; dual-pipeline; sampling flash architecture;

fLanguage

English

Publisher

ieee

Conference_Titel

Anti-Counterfeiting, Security and Identification (ASID), 2011 IEEE International Conference on

Conference_Location

Xiamen

ISSN

Pending

Print_ISBN

978-1-61284-631-6

Type

conf

DOI

10.1109/ASID.2011.5967433

Filename

5967433