An 8-bit 1MHz Successive Approximation Register (SAR) A/D with 7.98 ENOB

Author

Yafei Ye ; Liyuan Liu ; Fule Li ; Dongmei Li ; Zhihua Wang

Author_Institution

Instn. of Microelectron., Tsinghua Univ., Beijing, China

fYear

2011

fDate

24-26 June 2011

Firstpage

139

Lastpage

142

Abstract

An 8-bit 1MHz Successive Approximation Register (SAR) A/D has been developed. It employs two sampling bootstrapped switches, a charge redistribution DAC, a dynamic comparator and a digital control block. The presented ADC is fabricated in a 0.5μm CMOS process and the active core area is 0.5*1.0 mm². Measurement results show the A/D achieves 49.8dB peak SNDR and 68.7dB SFDR. The effect number of bits (ENOB) is 7.98. When the frequency of input signal is up to 5.477MHz, the A/D can also achieve more than 7 ENOB. The total power dissipates is 2.5-mW.

Keywords

CMOS analogue integrated circuits; analogue-digital conversion; bootstrap circuits; comparators (circuits); ADC; CMOS process; ENOB; SAR A/D; SFDR; SNDR; charge redistribution DAC; digital control block; dynamic comparator; effect number of bits; frequency 1 MHz; input signal; power 2.5 mW; sampling bootstrapped switches; size 0.5 mum; successive approximation register; word length 8 bit; Approximation methods; Arrays; Capacitors; Frequency measurement; Latches; Power demand; Registers; A/D; bootstrapped switch; charge redistribution; dynamic comparator; successive approximation register; undersampling;

fLanguage

English

Publisher

ieee

Conference_Titel

Anti-Counterfeiting, Security and Identification (ASID), 2011 IEEE International Conference on

Conference_Location

Xiamen

ISSN

Pending

Print_ISBN

978-1-61284-631-6

Type

conf

DOI

10.1109/ASID.2011.5967435

Filename

5967435