A SHA-less 12-bit 200-MS/s pipeline ADC

This paper describes a 12-bit, 200MS/s IF sampling pipeline A/D converter (ADC) that is implemented in SMIC 0.13 um CMOS process. The ADC has a sample-and-hold circuit that is integrated in the first pipeline stage, which removes the need for a dedicated sample-and-hold amplifier. In order to decrease the clock jitter effectively, a delay locked loop (DLL) circuit with duty cycle stabilization function is designed. A gain boosting miller compensation two stages OTA is used to achieve the sufficient gain; The use of the redundancy coding technique ease the requirement of the comparator´s offset voltage; On chip reference buffer and High speed LVDS interface are also designed in this ADC. The circuit occupies a chip area of 2mm × 2mm. Simulation result showed that the circuit achieves a SNDR of 73.2 dB and a SFDR of 92 dB at a 1.2V 70MHz sine wave input.