A CMOS low power, wide dynamic range RSSI with integrated AGC loop

Author

Lei, Qianqian ; Lin, Min ; Peng, Miao ; Chen, Zhiming ; Shi, Yin

Author_Institution

Dept. of Appl. Electron., Xi´´an Univ. of Technol., Xi´´an, China

fYear

2011

fDate

24-26 June 2011

Firstpage

173

Lastpage

176

Abstract

A low voltage low power CMOS limiter and received signal strength indicator (RSSI) with integrated automatic gain control (AGC) loop are designed using TSMC 0.13um CMOS technology. The limiter uses six-stage amplifier architecture for minimum power consideration achieves 56dB gain and 17MHz bandwidth. The RSSI has a dynamic range more than 60dB, and the RSSI linearity error is within ±0.5dB for an input power from -65dBm to -8dBm. The RSSI output voltage is from 0.2V to 1V and the slope of the curve is 14.28mV/dB. The RSSI with integrated AGC loop draws 1.5 mA (I and Q paths) from a 1.2V single supply, including limiters, RSSI and comparators.

Keywords

CMOS integrated circuits; amplifiers; automatic gain control; comparators (circuits); limiters; low-power electronics; integrated automatic gain control loop; low power CMOS limiter; received signal strength indicator; six-stage amplifier architecture; CMOS integrated circuits; Gain; Gain control; Limiting; Rectifiers; Resistors; Transistors; AGC; LA; RSSI; comparator;

fLanguage

English

Publisher

ieee

Conference_Titel

Anti-Counterfeiting, Security and Identification (ASID), 2011 IEEE International Conference on

Conference_Location

Xiamen

ISSN

Pending

Print_ISBN

978-1-61284-631-6

Type

conf

DOI

10.1109/ASID.2011.5967444

Filename

5967444