Partitioning and placement for multi-FPGA systems using genetic algorithms

One of the most important and difficult tasks in multi-FPGA systems design is partitioning. The main problems are related to the I/O pins and logic capacity of FPGAs. The number of pins available is a critical problem, because FPGA devices have such a reduced number of them compared with their logic capacity. In addition we must reserve some of the pins to interconnect parts of the circuit placed on non-adjacent FPGAs. Most of the previous works have been adapted from other VLSI areas, and hence, they disregard the specific features of these kind of circuit. A new method for solving the partitioning and placement problem in multi-FPGA systems is presented. We use graph theory to describe the circuit, then a classical genetic algorithm (GA) is applied with a problem-specific encoding. The algorithm preserves the original structure of the circuit and by means of a fuzzy technique it evaluates the I/O-pins consumption due to direct and indirect connections between FPGAs. We have used the Partitioning93 benchmarks described with the Xilinx Netlist Format (XNF). The results obtained show how genetic algorithms are capable of accomplishing successfully the partitioning and placement tasks while respecting the board constraints