• DocumentCode
    2500911
  • Title

    A fully depleted lean-channel transistor (DELTA)-a novel vertical ultra thin SOI MOSFET

  • Author

    Hisamoto, D. ; Kaga, T. ; Kawamoto, Y. ; Takeda, E.

  • Author_Institution
    Hitachi Ltd., Tokyo, Japan
  • fYear
    1989
  • fDate
    3-6 Dec. 1989
  • Firstpage
    833
  • Lastpage
    836
  • Abstract
    A fully depleted lean channel transistor (DELTA) having a gate structure and vertical ultrathin SOI (silicon-on-insulator) structure with selective field oxide is reported. In the deep submicron region, selective oxidation is useful for achieving SOI isolation. It provides a high-quality crystal and a Si-SiO/sub 2/ interface as good as those of conventional bulk single-crystal devices. Using experiments and simulation, it was shown that the gate structure of DELTA has effective channel controllability and its vertical ultrathin (<0.2- mu m) SOI structure provides superior device characteristics, e.g. the reduction of short channel effects, minimized subthreshold swing, and high transconductance. The DELTA layout is consistent with the conventional ULSI circuit layout. Thus, DELTA offers both consistency with conventional MOSFETs and good scalability As a 3-D device. As a result, DELTA provides a promising approach for MOSFET structures of less than 0.1 mu m in size.<>
  • Keywords
    VLSI; insulated gate field effect transistors; integrated circuit technology; semiconductor thin films; semiconductor-insulator boundaries; 0.1 micron; 3-D device; DELTA; DELTA layout; SOI isolation; Si-SiO/sub 2/ interface; channel controllability; consistency with conventional MOSFETs; conventional ULSI circuit layout; deep submicron region; device characteristics; fully depleted lean-channel transistor; gate structure; high transconductance; high-quality crystal; minimized subthreshold swing; reduction of short channel effects; scalability; scaling; selective field oxide; selective oxidation; vertical ultra thin SOI MOSFET; Controllability; Etching; Fabrication; Impedance; Laboratories; MOSFET circuits; Oxidation; Process design; Stress; Transconductance;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting, 1989. IEDM '89. Technical Digest., International
  • Conference_Location
    Washington, DC, USA
  • ISSN
    0163-1918
  • Print_ISBN
    0-7803-0817-4
  • Type

    conf

  • DOI
    10.1109/IEDM.1989.74182
  • Filename
    74182