Imperfectly connected 2D arrays for image processing

Author

Trotter, J.A. ; Moore, W.R.

Author_Institution

Dept. of Eng. Sci., Oxford Univ., UK

fYear

1989

fDate

21-23 June 1989

Firstpage

88

Lastpage

92

Abstract

An image processing architecture designed for ultralarge-scale and wafer-scale integration which uses a novel fault-tolerance strategy is described. The strategy overcomes many of the problems associated with configuring a 2D array from cells and spares with some kind of switching network. It provides a novel approach to fault tolerance because the primary mechanism for tolerating faults is neither hardware redundancy nor time redundancy but is a trade against processing resolution. The architecture provides a working, gracefully degrading array for image processing.<>

Keywords

computerised picture processing; fault tolerant computing; parallel architectures; 2D SIMD arrays; fault-tolerance strategy; graceful degradation; gracefully degrading array; image processing architecture; imperfectly connected 2D arrays; processing resolution; switching network; Circuit faults; Fabrication; Fault tolerance; Hardware; Image processing; Legged locomotion; Manufacturing; Redundancy; Silicon; Ultra large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Fault-Tolerant Computing, 1989. FTCS-19. Digest of Papers., Nineteenth International Symposium on

Conference_Location

Chicago, IL, USA

Print_ISBN

0-8186-1959-7

Type

conf

DOI

10.1109/FTCS.1989.105548

Filename

105548