Reliable design of high-speed cache and control store memories

The design of the cache and control store memories of the Tandem NonStop VLX processor is discussed. Service costs are reduced by using hot-standby sparing to improve the reliability of the large static RAM arrays. Detection, isolation, and spare substitution of failed RAMs are performed automatically without the disruption of normal processing. A control store design with sparing is described. A mathematical model is used to predict reliability improvements for the multiple arrays for each processor board. The model takes into account the selected repair policy which calls for replacing a board only on spare exhaustion or on the failure of nonspared logic. The success of the chosen approach is illustrated through model predictions as well as through field failure data.<>