DocumentCode
2502128
Title
A 7.7-ps CML using selective-epitaxial SiGe HBTs
Author
Ohue, Eiji ; Oda, Katsuya ; Hayami, Reiko ; Washio, Katsuyoshi
Author_Institution
Central Res. Lab., Hitachi Ltd., Kokubunji, Japan
fYear
1998
fDate
27-29 Sep 1998
Firstpage
97
Lastpage
100
Abstract
The fastest CML gate delay to date (7.7 ps) was achieved. This CML gate uses a fully-self-aligned SiGe-base HBT (with a 92 GHz cutoff frequency and a 108 GHz maximum oscillation frequency) with a selectively-implanted collector through the base
Keywords
Ge-Si alloys; bipolar logic circuits; current-mode logic; delays; epitaxial growth; heterojunction bipolar transistors; integrated circuit technology; logic gates; semiconductor materials; 108 GHz; 7.7 ps; 92 GHz; CML gate; SiGe; fully-self-aligned SiGe-base HBT; gate delay; selective-epitaxial SiGe HBTs; selectively-implanted collector; Boron; Cutoff frequency; Delay; Electrodes; Germanium silicon alloys; Heterojunction bipolar transistors; Parasitic capacitance; Silicon carbide; Silicon germanium; Substrates;
fLanguage
English
Publisher
ieee
Conference_Titel
Bipolar/BiCMOS Circuits and Technology Meeting, 1998. Proceedings of the 1998
Conference_Location
Minneapolis, MN
ISSN
1088-9299
Print_ISBN
0-7803-4497-9
Type
conf
DOI
10.1109/BIPOL.1998.741888
Filename
741888
Link To Document