DocumentCode
2502440
Title
A Memory Failure Pattern Analyzer for memory diagnosis and repair
Author
Lin, Bing-Yang ; Lee, Mincent ; Wu, Cheng-Wen
Author_Institution
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
fYear
2012
fDate
23-25 April 2012
Firstpage
234
Lastpage
239
Abstract
As VLSI technology advances and memories occupy more and more area in a typical SOC, memory diagnosis has become an important issue. In this paper, we propose the Memory Failure Pattern Analyzer (MFPA), which is developed for different memories and technologies that are currently used in the industry. The MFPA can locate weak regions of the memory array, i.e., those with high failure rate. It can also be used to analyze faulty-cell/defect distributions automatically. We also propose a new defect distribution model which has 1-12 times higher accuracy than other theoretical models. Based on this model, we propose a defect-spectrum-based methodology to identify critical failure patterns from failure bitmaps. These failure patterns can further be translated to corresponding defects by our memory fault simulator (RAMSES) and physical-level failure analysis tool (FAME). In an industrial case, the MFPA fits the defect distribution with the proposed model, which has 12 times higher accuracy than the Poisson distribution. With our model, it further identifies two special failure patterns from 132,488 faulty 4-Mb macros in 1.2 minutes.
Keywords
VLSI; failure analysis; fault diagnosis; integrated circuit reliability; maintenance engineering; parameter estimation; statistical distributions; storage management chips; system-on-chip; FAME; MFPA; Poisson distribution; RAMSES; SoC; VLSI technology; critical failure pattern identification; defect distribution model; defect-spectrum-based methodology; faulty-cell analysis; memory array; memory diagnosis; memory failure pattern analyzer; memory fault simulator; memory repair; physical-level failure analysis tool; storage capacity 4 Mbit; time 1.2 min; Redundancy; SOC; builtin-self-repair (BISR); memory diagnosis; redundancy analysis; yield improvement;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium (VTS), 2012 IEEE 30th
Conference_Location
Hyatt Maui, HI
ISSN
1093-0167
Print_ISBN
978-1-4673-1073-4
Type
conf
DOI
10.1109/VTS.2012.6231059
Filename
6231059
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