Thin-film silicon multichip technology

A hybrid technique that uses pretested integrated circuits mounted in holes etched in a silicon wafer is presented. The chips are interconnected with planar, thin-film metallization. This approach achieves near wafer-scale-integration (WSI) density, while allowing the use of separately fabricated and tested devices. Test wafers with three monolithic chips and one chip mounted in a hole were fabricated as proof of the concept. The key processes developed include fabrication of metallized and patterned wafers with etched holes, mounting of die in etched holes with planar topside topology, and deposition and patterning of the interlevel dielectric and metal links. A new organic resin derived from benzocyclobutene was evaluated as the interlevel dielectric. Wafers were thermally cycled to evaluate the compatibility of the materials and the process. No cracks or chip movement were observed after 50 cycles from -25°C to +85°C