DocumentCode
2502523
Title
2.5-Gbit/s SDH/SONET terminating circuit that uses low-power bipolar LSI technologies and multi-chip module technology
Author
Kawai, K. ; Koike, K. ; Koga, M. ; Takei, Y. ; Ichino, H.
Author_Institution
NTT, Japan
fYear
1998
fDate
27-29 Sep 1998
Firstpage
144
Lastpage
147
Abstract
A 2.5-Gbit/s 22-kGate SDH termination circuit has been developed that uses a power-management technique and has a multi-chip module design. Size and power are reduced to 1/10 and 1/6 that of currently available modules
Keywords
SONET; bipolar integrated circuits; digital communication; error statistics; high-speed integrated circuits; large scale integration; low-power electronics; monitoring; multichip modules; optical communication equipment; synchronous digital hierarchy; 2.5 Gbit/s; BER monitoring; MCM design; SDH/SONET terminating circuit; bit error rate; low-power bipolar LSI technologies; multi-chip module technology; power-management technique; Bit error rate; Circuits; Energy management; Information management; Large scale integration; Monitoring; Power system management; SONET; Synchronous digital hierarchy; Technology management;
fLanguage
English
Publisher
ieee
Conference_Titel
Bipolar/BiCMOS Circuits and Technology Meeting, 1998. Proceedings of the 1998
Conference_Location
Minneapolis, MN
ISSN
1088-9299
Print_ISBN
0-7803-4497-9
Type
conf
DOI
10.1109/BIPOL.1998.741909
Filename
741909
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