Title :
A 6-μm2 bipolar transistor using 0.25-μm process technology for high-speed applications
Author :
Imoto, T. Hash ; Kikuchi, T. ; Watanabe, K. ; Wada, S. ; Tamaki, Y. ; Kondo, M. ; Natsuaki, N. ; Owada, N.
Author_Institution :
Device Dev. Center, Hitachi Ltd., Tokyo, Japan
Abstract :
An advanced bipolar-process integration technology was developed and used for fabricating a 6-μm2-cell-size transistor with high cut-off frequency of 40 GHz. This process uses 0.25-μm lithography technology and shallow and deep trench isolations for reducing parasitic capacitance. ECL circuit performance is consequently improved up to 25 ps. A combination of low-energy ion-implantation and two-step base annealing was applied to form a low-leakage and shallow base junction. This technology was applied to an ultra-fast logic LSI, so we confirmed that the 0.25-μm technology can provide bipolar transistors with sufficient performance for use in ULSIs
Keywords :
ULSI; annealing; bipolar digital integrated circuits; bipolar logic circuits; emitter-coupled logic; high-speed integrated circuits; integrated circuit technology; ion implantation; isolation technology; large scale integration; lithography; 0.25 micron; 25 ps; ECL circuit performance; ULSI; advanced bipolar-process integration technology; bipolar transistor configuration; deep trench isolation; high-speed applications; lithography technology; low-energy ion-implantation; low-leakage junction; one quarter micron process technology; parasitic capacitance reduction; shallow base junction; shallow trench isolation; two-step base annealing; ultra-fast logic LSI; Annealing; Bipolar transistors; Circuit optimization; Cutoff frequency; Isolation technology; Large scale integration; Lithography; Logic; Parasitic capacitance; Ultra large scale integration;
Conference_Titel :
Bipolar/BiCMOS Circuits and Technology Meeting, 1998. Proceedings of the 1998
Conference_Location :
Minneapolis, MN
Print_ISBN :
0-7803-4497-9
DOI :
10.1109/BIPOL.1998.741911
