Hybrid Communication Reconfigurable Network on Chip for MPSoC

Shrinking transistor sizes and recent trends toward many-core chips have heightened the need for an efficient on-chip communication network to integrate various cores. However, buses and point-to-point interconnection will not result in scalability, modularity, and explicit parallelism, as well as may suffer great performance bottleneck. While state-of-art packet-switched network increases the communication costs and is incapable of performing multicast service. In addition, the emergence of reconfigurable system needs a flexible and application-specific architecture which could dynamically customize the systems. HCR-NoC (Hybrid-Communication Reconfigurable Network-on-Chip) is proposed in this paper, which could dynamically reconfigure MPSoC architecture based on buses traffic. To satisfy different communication services, we use a TDMA shared bus for inter-cluster communication in a designable framework, which enables topology reconfiguration upon regular physical network topology. An analytical verification tool is presented to simulate HCR-NoC system performance. Finally, the evaluations of HCR-NoC using Multimedia benchmarks show that significant reduction in power and area as compared to optimal mesh architecture NoC.