DocumentCode :
2502978
Title :
Delay test resource allocation and scheduling for multiple frequency domains
Author :
Arslan, Baris ; Orailoglu, Alex
Author_Institution :
Comput. Sci. & Eng., Univ. of California, San Diego, La Jolla, CA, USA
fYear :
2012
fDate :
23-25 April 2012
Firstpage :
114
Lastpage :
119
Abstract :
As the number of frequency domains aggressively grows in today´s SOCs, the delivery of high delay test quality across numerous frequency domains while meeting test budgets is crucial. This goal necessitates not only the consideration of fault coverage but also the distinct characteristics of each domain such as frequency and the distribution of path lengths and, additionally, the delay test quality tradeoffs across these domains. This paper proposes a method to identify the optimal test time allocation per domain based on the distinct characteristics of each in order to minimize overall delay defect escape level. The proposed method not only considers test time allocation but also concurrent scheduling of domains to optimize the delay test quality for SOCs that support the testing of multiple frequency domains in parallel.
Keywords :
integrated circuit testing; scheduling; system-on-chip; SOC; delay defect escape level; delay test quality; delay test resource allocation; delay test resource scheduling; fault coverage; multiple frequency domain; path length; test time allocation; Circuit faults; Delay; Estimation; Frequency domain analysis; Resource management; System-on-a-chip; Testing; delay test; test quality optimization; test scheduling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium (VTS), 2012 IEEE 30th
Conference_Location :
Hyatt Maui, HI
ISSN :
1093-0167
Print_ISBN :
978-1-4673-1073-4
Type :
conf
DOI :
10.1109/VTS.2012.6231089
Filename :
6231089
Link To Document :
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