Test of phase interpolators in high speed I/Os using a sliding window search

Conventional test for high speed serial links requires expensive test equipment to meet the standard <; 10^-12 bit error rate (BER) requirement. Although timing margining loop-back tests are cost effective, phase interpolator (PI) circuitry needs to be tested for test completeness. Our method provides an efficient linearity test capability for the PI circuitry. In the proposed scheme, a sliding window search algorithm is used to extract differential nonlinearity (DNL) and integral nonlinearity (INL), based on a jitter distribution obtained from undersampling. Various simulations were performed to evaluate the accuracy and robustness of the method. They indicate that the proposed algorithm provides an accurate estimation of linearities of the PI. We also implemented our algorithm in a conventional low cost high volume manufacturing (HVM) tester platform to show feasibility and validity of the proposed technique.