Title :
Enhancing testability by structured partial scan
Author :
Wohl, P. ; Waicukauski, J.A. ; Colburn, J.E.
Abstract :
Full scan designs are widely used for their indisputable benefits of predictably high test coverage, diagnosis and debug. However, for high-performance designs the cost of scan - area and delay - is not acceptable and partial scan is used instead. Unfortunately, partial scan significantly increases test generation complexity. We define a structured partial scan design methodology and specific test generation enhancements, which significantly enhance test coverage and reduce test data and cycles. Selective design areas use special types of nonscan cells which can capture a value in the last few scan load cycles. Combinational test generation is extended to work with this structured partial scan design, resulting in higher coverage and fewer patterns. Experimental results on industrial designs show consistent testability benefits.
Keywords :
automatic test pattern generation; boundary scan testing; design for testability; logic testing; combinational test generation; full scan design; high test coverage; high-performance design; industrial design; structured partial scan design; test cycles; test generation complexity; test generation enhancement; Automatic test pattern generation; Circuit faults; Clocks; Complexity theory; Decoding; Load modeling; Logic gates;
Conference_Titel :
VLSI Test Symposium (VTS), 2012 IEEE 30th
Conference_Location :
Hyatt Maui, HI
Print_ISBN :
978-1-4673-1073-4
DOI :
10.1109/VTS.2012.6231095