A SMT-based diagnostic test generation method for combinational circuits

Author

Prabhu, Sarvesh ; Hsiao, Michael S. ; Lingappan, Loganathan ; Gangaram, Vijay

Author_Institution

Dept. of Electr. & Comput. Eng., Virginia Tech, Blacksburg, VA, USA

fYear

2012

fDate

23-25 April 2012

Firstpage

215

Lastpage

220

Abstract

A diagnostic test pattern generator using a Satisfiability Modulo Theory (SMT) solver is proposed. Rather than targeting a single fault pair at a time, the proposed SMT approach can distinguish multiple fault pairs in a single instance. Several heuristics are proposed to constrain the SMT formula to further reduce the search space, including fault selection, excitation constraint, reduced primary output vector, and cone-of-influence reduction. Experimental results for the ISCAS85 and full-scan versions of ISCAS89 benchmark circuits show that fewer diagnostic vectors are generated compared with conventional diagnostic test generation methods. Up to 73% reduction in the number of vectors generated can be achieved in large circuits.

Keywords

combinational circuits; computability; fault diagnosis; logic testing; ISCAS85 version; ISCAS89 benchmark circuit; SMT formula; SMT-based diagnostic test generation method; combinational circuit; cone-of-influence reduction; diagnostic test pattern generator; diagnostic vectors; excitation constraint; fault selection; multiple fault pair; reduced primary output vector; satisfiability modulo theory solver; Automatic test pattern generation; Circuit faults; Context; Integrated circuit modeling; Logic gates; Multiplexing; Vectors; Satisfiability Modulo theory(SMT); diagnostic test pattern generation; fault distinguishing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium (VTS), 2012 IEEE 30th

Conference_Location

Hyatt Maui, HI

ISSN

1093-0167

Print_ISBN

978-1-4673-1073-4

Type

conf

DOI

10.1109/VTS.2012.6231105

Filename

6231105