• DocumentCode
    2503304
  • Title

    Net diagnosis using stuck-at and transition fault models

  • Author

    Zhao, Lixing ; Agrawal, Vishwani D.

  • Author_Institution
    FutureWei Tecnologies, Inc., Santa Clara, CA, USA
  • fYear
    2012
  • fDate
    23-25 April 2012
  • Firstpage
    221
  • Lastpage
    226
  • Abstract
    Given the test output from a defective digital circuit, we identify one or more faulty signal nets that may have caused the observed output results. Although we make no assumption about the actual defect, our diagnosis is based upon a dictionary pre-generated by simulating the test vectors for their detection of collapsed single stuck-at and transition faults at each primary output. First, novel three-stage candidate filtering system and candidate ranking system are proposed to reduce and rank candidate faults. A more balanced ranking method compared to previous works and a ranking strategy which combined both overall and per-test performance together are used in these two systems. Then, the ranked candidate list is expanded by uncollapsing faults. A rank for every candidate net is calculated based on the number of top-ranked suspected faults on it. Experiments were conducted by injecting multiple stuck-at or transition delay faults on either single or double nets in certain ISCAS85 circuit. When tests generated by targeting single stuck-at and transition faults were used, our diagnosis algorithm shows good diagnosability and resolution in identifying single and double faulty nets.
  • Keywords
    digital circuits; fault diagnosis; logic circuits; logic testing; ISCAS85 circuit; balanced ranking method; candidate ranking system; digital circuit; net diagnosis; stuck-at fault model; test vector; three-stage candidate filtering system; transition fault model; Benchmark testing; Circuit faults; Fault diagnosis; Indexes; Integrated circuit modeling; Mathematical model; Pattern matching; digital circuit testing; fault diagnosis; stuck-at fault test; transition fault test;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Test Symposium (VTS), 2012 IEEE 30th
  • Conference_Location
    Hyatt Maui, HI
  • ISSN
    1093-0167
  • Print_ISBN
    978-1-4673-1073-4
  • Type

    conf

  • DOI
    10.1109/VTS.2012.6231106
  • Filename
    6231106