Power delay tradeoff using the genetic algorithm

Author

Sosa, Javier ; Montiel-Nelson, Juan A. ; Nooshabadi, Saeid

Author_Institution

Inst. Univ. de Microelectron. Aplic., Univ. de Las Palmas de Gran Canaria, Las Palmas, Spain

fYear

2009

fDate

28-30 Sept. 2009

Firstpage

1344

Lastpage

1347

Abstract

This paper presents a novel methodology to obtain the entire power versus delay tradeoff curve for the critical paths of a combinational logic circuit in a very efficient way using genetic algorithm (GA). In order to evaluate the proposed GA method a wide set of two-level and multi-level networks from the MCNC´91 benchmark suite was processed. The proposed optimization using the GA methodology is several times better than linear programming (LP) technique in terms of CPU time. On the other hand the minimum power dissipation obtained by GA and LP methods are very close to each other to within 0.3%.

Keywords

CMOS integrated circuits; genetic algorithms; linear programming; CMOS technology scaling; GA method; MCNC´91 benchmark suite; combinational logic circuit; delay tradeoff curve; genetic algorithm; linear programming technique; minimum power dissipation; multilevel networks; power delay tradeoff; two-level networks; CMOS technology; Combinational circuits; Delay; Energy consumption; Genetic algorithms; Linear programming; Optimization methods; Paper technology; Scheduling; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications and Information Technology, 2009. ISCIT 2009. 9th International Symposium on

Conference_Location

Icheon

Print_ISBN

978-1-4244-4521-9

Electronic_ISBN

978-1-4244-4522-6

Type

conf

DOI

10.1109/ISCIT.2009.5341062

Filename

5341062