Novel low-power 1-bit full adder design

This paper propose a 1-bit low-power full adder that is designed by taking the advantage of the concept of pass-transistor logic and the concept of dual-threshold domino logic. The concept of pass-transistor logic is used to design the circuit generating the sum signal such that the number of transistors can be reduced. The concept of dual-threshold domino logic is adapted to design the circuit generating the carryout signal such that the operation can be speeded up. This full adder was designed with a TSMC 0.18-mum 1P6M CMOS process. The HSPICE simulation results show that this design achieves a superior performance with a power-delay product of 48.98 fJ for the SUM circuit and 16.19 fJ for the CARRYOUT circuit at 1.8-V supply voltage.