Title :
A memoryless Viterbi decoder for LTE systems
Author :
Yu, Chu ; Su, Yu-Shan ; Lin, Bor-Shing ; Cheng, Po-Hsun ; Chen, Sao-Jie
Author_Institution :
Dept. of Electron. Eng., Nat. Ilan Univ., Ilan, Taiwan
Abstract :
This paper presents a novel memoryless Viterbi decoder (VD) with a 4-level soft decision for long term evolution (LTE) systems. Based on the proposed architecture, the survivor memory can be eliminated totally, which will significantly reduce 50% of the total power dissipation. Finally, the proposed design consumes approximately 23.4K gates using 0.18 μm CMOS technology, and its power consumption is approximately 7.5 mW at 80 MHz.
Keywords :
CMOS integrated circuits; Long Term Evolution; UHF integrated circuits; Viterbi decoding; integrated circuit design; 4-level soft decision; CMOS technology; LTE system; Long Term Evolution; VD; frequency 80 MHz; memoryless Viterbi decoder; power consumption; power dissipation; size 0.18 mum; CMOS integrated circuits; Decoding; Educational institutions; Memory architecture; Viterbi algorithm; Wireless communication; Viterbi decoder; low power; the survivor memory;
Conference_Titel :
Consumer Electronics (GCCE), 2012 IEEE 1st Global Conference on
Conference_Location :
Tokyo
Print_ISBN :
978-1-4673-1500-5
DOI :
10.1109/GCCE.2012.6379940
