Title :
Flip chip attach with thermoplastic electrically conductive adhesive
Author :
Gaynes, Michael ; Kodnani, Ramesh ; Pierson, Mark ; Hoontrakul, Patricia ; Paquette, Matthew
Author_Institution :
IBM Corp., Endicott, NY, USA
Abstract :
A set of processes has been developed and demonstrated to interconnect flip chips with an electrically conductive adhesive material to laminates. Paste deposition uses a photolithography process to define room temperature stable thermoplastic conductive adhesive bumps that are 0.2 mm in diameter and 0.1 mm high. Photobumping is done at wafer level, and dicing yields chips that are ready for attachment to a carrier. Chip bonding process development defined a process window and identified an optimal process point. Repeatable tensile bond strengths between 10 and 14 MPa can be achieved. Fracture mode typically occurs near an interface but in the joint material. Bonding temperature, pressure, and pressure on cool-down (to 120°C) were identified as key process variables. The optimum bonding process point is applying one MPa to the chip, while heating to 235°C. Pressure is maintained for 30 seconds at temperature and until cooled to 70°C. These optimum bond parameters resulted in bond lines of 0.05±0.005 mm. The harshest stress test is deep thermal cycling for both blanket and stitched chip designs. The interconnect performance on the blanket chip is comparable to soldered flip chip on laminate. The interconnect performance on the stitch chip is less robust. It is believed that reaction between the photobumping stripper and the polyimide passivation results in a weak interface between the adhesive bump and card metallurgy. Results from stress testing demonstrate the design feasibility of electrically conductive adhesive interconnects for flip chip attach to laminates
Keywords :
adhesives; conducting polymers; cooling; failure analysis; filled polymers; flip-chip devices; fracture; integrated circuit design; integrated circuit interconnections; integrated circuit packaging; integrated circuit testing; microassembling; passivation; photolithography; polymer films; tensile strength; thermal stresses; 0.045 to 0.055 mm; 0.1 mm; 0.2 mm; 120 C; 235 C; 70 C; adhesive bump-card metallurgy interface; blanket chip design; bond lines; bonding pressure; bonding temperature; carrier attachment; chip bonding process development; cool-down pressure; cooling; deep thermal cycling; design feasibility; dicing; electrically conductive adhesive interconnects; electrically conductive adhesive material; flip chip attach; flip chip interconnects; fracture mode; heating; interconnect performance; laminates; optimal process point; optimum bond parameters; optimum bonding process point; paste deposition; photobumping stripper; photolithography process; polyimide passivation; process variables; process window; repeatable tensile bond strengths; room temperature stable thermoplastic conductive adhesive bumps; stitch chip; stitched chip design; stress test; stress testing; thermoplastic electrically conductive adhesive; wafer level photobumping; weak interface; Bonding processes; Conducting materials; Conductive adhesives; Flip chip; Laminates; Lithography; Temperature; Testing; Thermal stresses; Wafer bonding;
Conference_Titel :
Adhesive Joining and Coating Technology in Electronics Manufacturing, 1998. Proceedings of 3rd international Conference on
Conference_Location :
Binghamton, NY
Print_ISBN :
0-7803-4934-2
DOI :
10.1109/ADHES.1998.742034