A study of sub-threshold digital circuits for wireless communication systems

Digital circuit designs in sub-threshold region have been studied in recent years. Their works focus on special purpose for some digital applications in low frequency. This paper proposed modeling analysis of each CMOS logic cell operating at sub-threshold region. We explore the delays and power dissipation of logic cell and make scaled factors mapping from typical voltage to sub-threshold voltage conditions. We evaluated the minimum requirement for 4 bits, 6 bits and 10 bits orthogonal frequency division multiplexing (OFDM) demodulator to operate in sub-threshold region. The simulation results are characteristics of OFDM wireless communication system when it operates at low voltage. It also clearly shows that low voltage is not a barrier for large-scale digital circuits to operate under the threshold voltage.