A 256 kbit SOI-full-CMOS-SRAM

Author

Gotou, H. ; Sekiyama, A. ; Seki, T. ; Nagai, S. ; Suzuki, N. ; Hayasaka, M. ; Matsukawa, Y. ; Miyazima, M. ; Kobayashi, Y. ; Enomoto, S. ; Imaoka, K.

Author_Institution

Fujitsu Ltd., Tokyo, Japan

fYear

1989

fDate

3-6 Dec. 1989

Firstpage

912

Lastpage

913

Abstract

The authors describe a 256-kb SOI full-CMOS SRAM which has a wide operation range of supply voltage, 2-6 V. Full-bit-pass devices have been obtained using bonding SOI (silicon-on-insulator) wafers. The key process parameters are listed. The leakage current of the n- or p-type SOI transistor is less than the measurement limit, 0.1 pA/ mu m. The subthreshold swings are 73 mV/decade for n-channel and 82 mV/decade for p-channel transistors. These characteristics are better than or the same as those of the bulk transistor. The SOI device has a 30% shorter address access time than the bulk device at 2-V supply voltage.<>

Keywords

CMOS integrated circuits; SRAM chips; semiconductor-insulator boundaries; 2 to 6 V; 256 kbit; SOI-full-CMOS-SRAM; address access time; bonded SOI wagers; full-bit-pass devices; leakage current; n-channel transistors; p-channel transistors; process parameters; subthreshold swings; supply; supply voltage; Capacitance; Delay effects; Low voltage; MOSFET circuits; Oxidation; Ring oscillators; Silicon compounds; Very large scale integration; Voltage-controlled oscillators; Wafer bonding;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1989. IEDM '89. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-0817-4

Type

conf

DOI

10.1109/IEDM.1989.74204

Filename

74204