Underfill of flip chip on laminates: simulation and validation

Author

Nguyen, L. ; Quentin, C. ; Fine, P. ; Cobb, B. ; Bayyuk, S. ; Yang, H. ; Bidstrup-Allen, S.A.

Author_Institution

Nat. Semicond. Corp., Santa Clara, CA, USA

fYear

1998

fDate

28-30 Sep 1998

Firstpage

312

Lastpage

320

Abstract

The flow characteristics of a number of underfills were evaluated with quartz dies of different patterns and pitches bonded on different substrate surfaces. Perimeter, mixed array, and full array patterns were tested. Observations on the flow front uniformity, streaking, voiding, and filler segregation were collected. The information was compared with the resulted predicted by a new simulation code, PLICE-CAD (plastic IC encapsulation-computer aided design), under DARPA-funded development. The two-phase model of the combined resin and air takes into account geometrical factors such as bumps and die edges, together with boundary conditions in order to track the propagation of the flow fronts accurately. The two-phase flow field is based on the volume-of-fluid (VOF) methodology embedded in a general-purpose 3D flow solver

Keywords

chip-on-board packaging; circuit CAD; circuit simulation; encapsulation; filled polymers; flip-chip devices; flow simulation; integrated circuit packaging; microassembling; plastic packaging; voids (solid); PLICE-CAD simulation code; SiO₂; boundary conditions; die edges; filler segregation; flip chip; flip chip bumps; flow characteristics; flow front propagation; flow front streaking; flow front uniformity; full array patterns; general-purpose 3D flow solver; laminate substrates; mixed array patterns; perimeter array patterns; plastic IC encapsulation-computer aided design; quartz die bonding; quartz die patterns; quartz die pitches; quartz dies; simulation; simulation code; substrate surfaces; two-phase flow field; two-phase model; underfill; underfill validation; underfills; voiding; volume-of-fluid methodology; Bonding; Charge coupled devices; Charge-coupled image sensors; Flip chip; Laminates; Optical devices; Ovens; Resins; Temperature; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Adhesive Joining and Coating Technology in Electronics Manufacturing, 1998. Proceedings of 3rd international Conference on

Conference_Location

Binghamton, NY

Print_ISBN

0-7803-4934-2

Type

conf

DOI

10.1109/ADHES.1998.742047

Filename

742047