Title :
Time-multiplexed on-chip delay measurement for dependable high-speed digital LSIs
Author :
Katoh, Kentaroh ; Itagaki, Kei ; Hoshina, Shinichiro
Author_Institution :
Dept. of Electr. Eng., Tsuruoka Nat. Coll. of Technol., Yamagata, Japan
Abstract :
High-speed digital LSIs such as CPU, graphic processing LSI, and System-on-a-chip, are indispensable for all the today´s consumer electrics. However, such today´s high performance LSIs require careful debugging for timing related errors and high quality delay fault testing for the dependability. This paper presents time-multiplexed on-chip delay measurement to realize fast and high quality timing error debugging and delay fault testing. According to the experimental result, the measurement time of the proposed method is 2.5 % of the conventional one.
Keywords :
large scale integration; CPU; consumer electrics; dependability; dependable high speed digital LSI; graphic processing LSI; high quality delay fault testing; high quality timing error debugging; system on chip; time multiplexed on chip delay measurement; timing related errors; Clocks; Debugging; Delay; System-on-a-chip; Testing; digital LSI; time-multiplexed on-chip delay measurement; timing error;
Conference_Titel :
Consumer Electronics (GCCE), 2012 IEEE 1st Global Conference on
Conference_Location :
Tokyo
Print_ISBN :
978-1-4673-1500-5
DOI :
10.1109/GCCE.2012.6379966
