Modeling and Separate Extraction Technique for Gate Bias-Dependent Parasitic Resistances and Overlap Length in MOSFETs

We report a technique for separate extraction of extrinsic source/drain (S/D) resistances (R_Se/R_De) and gate bias (V_GS)-dependent but channel length (L)-independent intrinsic source/drain (R_Si/R_Di) resistances for the overlap region in MOSFETs. For extraction of the overlap length (L_ov) in the heavily doped S/D regions, an analytical capacitance model for the depletion region is employed with the gate-to-source and gate-to-drain capacitance-voltage (C_G-S, C_G-D) characteristics. After verifying the extracted overlap length through a 2-D technology computer-aided design simulation, we successfully extract V_GS-dependent R_Si = 0.9~3.7 Ω and R_Di = 1.0~3.9 Ω in an n-channel MOSFET with W = 140 μm and L = 0.35 μm. In addition, V_GS- and L-independent extrinsic S/D resistances are separately extracted to be R_Se = 5.1 Ω and R_De = 5.0 Ω, respectively.