VLSI circuit design concept for parallel iterative algorithms in nanoscale

Modern VLSI manufacturing technology has kept shrinking down to the nanoscale level with a very fast trend. Integration with the advanced nano-technology now makes it possible to realize advanced parallel iterative algorithms directly which was almost impossible 10 years ago. In this paper, we want to discuss the influences of evolving VLSI technologies for iterative algorithms and present design strategies from an algorithmic and architectural point of view. We can simplify the parallel implementation of the iterative algorithm (i.e., processor elements of the multiprocessor array) in any way as long as the convergence is guaranteed. However, the modification of the algorithm (processors) usually increases the number of required iterations which also means that the switch activity of interconnects is increasing. We implemented a 3times3 Jacobi EVD array with the mu-CORDIC PE in both 0.18 mum and 45 nm technologies in order to further study the trade-off between the performance/complexity of processors and the load/throughput of interconnects. Our experimental results show that using the mu-CORDIC PE is beneficial concerning the design criteria since it yields smaller chip area, faster overall computation timing and less energy consumption per operation than the full CORDIC PE.