RDRAM/spl reg/ channel design with 32-bit 4.8 GB/s memory modules

Author

Huang, Ching-Chao ; Nguyen, David ; Oh, Kyung Suk Dan ; Yip, Wai-Yeung ; Secker, David

Author_Institution

Rambus Inc., Los Altos, CA, USA

fYear

2002

fDate

21-23 Oct. 2002

Firstpage

19

Lastpage

22

Abstract

This paper describes an RDRAM channel design with novel 32-bit RIMM/spl reg/ modules which deliver a data bandwidth of 4.8 GB/s at 600-MHz clock frequency. Only two RIMM modules are needed for the entire 32-bit, 2-channel design, reducing both the board space and manufacturing cost. Detailed physical architecture, design optimization, and modeling and simulation methodology are presented. Numerous simulations with multi-stage calibration are automated to ensure ample voltage and timing margins for a robust design.

Keywords

DRAM chips; circuit optimisation; circuit simulation; integrated circuit design; integrated circuit modelling; integrated circuit packaging; memory architecture; modules; timing; 32 bit; 4.8 GB/s; 600 MHz; RDRAM channel design; RIMM modules; board space; clock frequency; data bandwidth; design optimization; manufacturing cost; memory modules; modeling; multi-stage calibration; physical architecture; simulation methodology; timing margins; voltage margins; Bandwidth; Calibration; Clocks; Costs; Design optimization; Frequency; Manufacturing; Robustness; Timing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Performance of Electronic Packaging, 2002 IEEE 11th Topical Meeting on

Conference_Location

Monterey, CA, USA

Print_ISBN

0-7803-7451-7

Type

conf

DOI

10.1109/EPEP.2002.1057874

Filename

1057874