Electrical modeling of high-speed source synchronous communication

Author

Rubin, B.J. ; de Araujo, D.N. ; Pham, N. ; Cases, M.

Author_Institution

IBM Res. Div., T.J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

2002

fDate

21-23 Oct. 2002

Firstpage

23

Lastpage

26

Abstract

The basic electrical package modeling issues for source synchronous communication are discussed, and modeling techniques are reviewed. A new fine-grained approach that include all essential package features are discussed, with emphasis on coupled and delta-I noises and the interactions between the clock and the signal bus waveforms.

Keywords

circuit noise; circuit simulation; clocks; digital communication; integrated circuit interconnections; integrated circuit modelling; integrated circuit packaging; integrated memory circuits; memory architecture; clock/signal bus waveform interactions; coupled noise; delta-I noise; electrical package modeling; fine-grained approach; high-speed source synchronous communication; memory architecture; modeling techniques; package features; Centralized control; Clocks; Crosstalk; Drives; Electronics packaging; Frequency; Jitter; Microprocessors; Power distribution; Signal design;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Performance of Electronic Packaging, 2002 IEEE 11th Topical Meeting on

Conference_Location

Monterey, CA, USA

Print_ISBN

0-7803-7451-7

Type

conf

DOI

10.1109/EPEP.2002.1057875

Filename

1057875